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Details of 13.1 Software and IP Changes
New and Modified Design Rule Checks
The following is a list of new and modified Design Rule Check (DRCs) in PlanAhead 13:
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Attribute DRCs
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AVAL - Checks for invalid attribute values.
ADEF - Checks for undefined attribute values.
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Bank DCI Cascade DRC
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DCICIOSTD - Checks that the DCI Cascade constraint is legal.
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Bank I/O Standard DRC
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VCCAUX2 - Warns of any requirements on LVPECL_33 and TMDS_33
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ChipScope DRCs
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CSUC - Checks for unconnected channels.
CSCL - Checks for non-clock nets that are clocking clocked elements
CSBR - Device block RAM resources exceeded.
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DSP48 DRCs
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DPCA - Checks the DSP48 cascade.
DPREG - Checks for DSP48 asynchronous feedback.
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FIFO DRC
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FSYN - Checks for synchronous FIFO.
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IOB DRC
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OPCSLR - Checks for part compatibility between monolithic and multi-die
devices.
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Placer DRCs
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PLCR - Placement constraint to check for clock regions.
PLCK - Check clock placement for valid location.
PLDL - Placement constraint for I/Os.
PLVP - Checks for valid LOC placement
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RAMB DRC
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RAMB - Check for clock restrictions for READ_FIRST mode.
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Required Pin DRC
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REQP - Checks for required pins that are not connected.
Implementation and Analysis Enhancements
PlanAhead 13 contains the following Implementation and Analysis enhancements.
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Implementation Enhancements
The Implementation enhancements include:
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Ease of file ordering for Implementation Runs.
Ability to store Run-specific constraints in a specified UCF file.
Once you implement a design, PlanAhead automatically loads/stores the
constraints from that Run in a run-specific UCF.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
www.xilinx.com
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